|
6U VPX mSATAܔ惦
̫ٿƼ˾
һ忨
ԓa(chn)Ʒϵ˾аl(f)ژ˜6U VPXܘ
a(chn)Ʒ
惦8TB
x(xi)ʽRAID0 ,x(xi)2GB/s
·x4 SRIO@5Gbps/Lane
· x4 PCIe@5Gbps/Lane
d4GB DDR3 SDRAM
d 2w 128MB NorFlash
·1000Base-Tӿ
VITA46.0 VPX Base Standard
a(chn)ƷҎ
̎ | Ƭ Xilinx FPGA XC7K325T-2FFG900I |
惦 | ÿƬFPGADDR3 SDRAM 256M x 64bit |
ÿƬFPGA BPI Flash 128MBڳd | |
8(g)mSATAP(pn) @ 6Gbps/lane _8TB | |
VPXӿ | P0?jin)ԴϵyλƽЧSM(xin)IIC |
P1ĽMx4 SRIO @ 5Gbps/Lane | |
P2ɽMx4 PCIe @ 5Gbps/Lane,һ(g)ǧ̫W(wng) 10/100/1000 Base-T | |
P332LVDS | |
P432LVDS | |
ǰ | һ(g)ǧ̫W(wng) |
ɂ(g)Դָʾ | |
һ(g)ϵyλI | |
ɂ(g)FPGAքe4(g)LEDsǰڠB(ti)ָʾ{ԇ | |
Ƭg(lin) | ɂ(g)FPGA (sh)F72LVDS(lin) |
ض | -40~ 70C |
Ҫ | ԴDC12V~5A |
ɢ᷽ʽ | L(fng)ɢ |
OpenVPX˜OӋĸܹ̑B(ti)惦
һ
VPX-ST6UϵǰVITA46OpenVPX˜OӋĸܹ̑B(ti)惦,LSI2308, ֧8(g)SSDģK,mڸܺ惦
c(din)
6U ̑B(ti)惦
֧VITA65 OpenVPX
PCIE3.0ӿ,PCIE2.0
֧ RAID 0 1 10
x(xi)4GB/S
֧512G, 1 2 4 8T
߿ɿ
ȲYD
Ҏ
惦 | 8 6GB/S mSATA SSD |
̎ | LSISAS2308 |
ģK | 6Gb/s |
ӿ | X8 PCIe3.0 ¼ |
ӿ | 8Gb/s |
8TB | |
x | 4GB/S |
(xi) | 4GMB/S |
IOPS (x/(xi)) | 350K/300K |
ϵyRaid | 0 1 10 |
(dng)֧ | Windows |
\늉 | +12V |
| 36 W |
o(w)Ϲr(sh)g | >200,0000Сr(sh) |
h(hun) | ض-20C to 75C5 to 90% Y |
惦h(hun) | ض-45C to 105 5 to 90% Y |
VPX-ST6U-1T | VPX-ST6U-2T | VPX-ST6U-4T | |
x (1MB) | 3.5GB/s | 3.8GB/s | 3.8GB/s |
(xi)(1MB) | 2.4GB/s | 3.0GB/s | 3.2GB/s |
SCx(512B) | 345300 | 355300 | 358300 |
SC(xi) (512B) | 240200 | 248200 | 254200 |
SCx(4K) | 341900 | 350900 | 355700 |
SC(xi) (4K) | 294800 | 325300 | 328300 |
xL(fng)(wn)r(sh)g | 57s | 57s | 53s |
(xi)L(fng)(wn)r(sh)g | 20s | 20s | 18s |
ӿڶx
ߴ
̫ٿƼ˾