ADI AD9739A FMC卡和Xilinx SP605參考設計方案

發(fā)布時(shí)間:2012-8-2 00:47    發(fā)布者:1770309616
關(guān)鍵詞: AD9739A , ADI , FMC卡 , SP605 , Xilinx
ADI公司的AD9739A FMC卡是Xilinx SP605, ML605或KC705評估板的子板.兩者組成的平臺能把MPEG TS流轉換成IF或RF信號(單路或多路),并支持大多數數字電視標準(DVB-C,J.83B, DVB-T, ATSC, DVB-S, ...),并可用來(lái)評估多種IP核如DVB-C J.83 Annex A/C 調制器,J.83 B有線(xiàn)調制器,DVB-T/H調制器, ATSC調制器,DVB-S調制器等. 主要用在MVD IP核(TS處理,調制,RF上變換).本文介紹了AD9737A/AD9739A產(chǎn)品亮點(diǎn)和主要特性,功能框圖以及ADI AD9739A FMC卡+ Xilinx SP605評估平臺框圖,主要特性和ADI AD9739A FMC評估板電路圖.

The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS.

By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A.

The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.

The AD9737A/AD9739A are manufactured on a 0.18 μm CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics.

AD9737A/AD9739A產(chǎn)品亮點(diǎn):

1. Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone.

2. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mix-mode operation.

3. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS.

4. On-chip controllers manage external and internal clock domain skews.

5. Programmable differential current output with an 8.66 mA to 31.66 mA range.

AD9737A/AD9739A主要特性:

Direct RF synthesis at 2.5 GSPS update rate

DC to 1.25 GHz in baseband mode

1.25 GHz to 3.0 GHz in mix-mode

Industry leading single/multicarrier IF or RF synthesis

Dual-port LVDS data interface

Up to 1.25 GSPS operation

Source synchronous DDR clocking

Pin compatible with the AD9739

Programmable output current: 8.7 mA to 31.7 mA

Low power: 1.1 W at 2.5 GSPS

AD9737A/AD9739A 應用:

Broadband communications systems

DOCSIS CMTS systems

Military jammers

Instrumentation, automatic test equipment

Radar, avionics

圖1.AD9737A/AD9739A功能框圖

The AD9739A is a 14-bit, 2.5 GSPS high performance RF DAC capable of synthesizing wideband signals with up to 1.25GHz of bandwidth. This reference design includes a single tone sine generator (DDS) and allows programming the device and monitoring it’s internal status registers. It also programs the ADF4350 clock chip which can generate a 1.6GHz to 2.5GHz clock for the AD9739A from the on-board 25MHz crystal. An alternate clock path using an ADCLK914 is available for driving the clock externally.

圖2.AD9739A FMC評估板外形圖

Eval Board w/ an FMC connector for Xilinx based FPGA development

The Analog Devices AD9739A FMC card is a daughter board that can be used in addition to Xilinx SP605, ML605 or KC705 evaluation boards.

The resulting platform includes all necessary components for the evaluation of most of our IP cores.           
圖3.ADI AD9739A FMC卡+ Xilinx SP605評估平臺框圖

                     
                     

圖4.ADI AD9739A FMC卡+ Xilinx SP605評估平臺外形圖

ADI AD9739A FMC卡+ Xilinx SP605評估平臺主要特性:

The evaluation platform converts an MPEG TS stream into an IF or RF signal (single or multi-channel) and supports most of the digital TV standards (DVB-C, J.83B, DVB-T, ATSC, DVB-S, ...).

The evaluation platform can be used for the evaluation of our IP cores:

DVB-C J.83 Annex A/C modulator

J.83 B cable modulator

DVB-T/H modulator

ATSC modulator

DVB-S modulator

Digital RF Up Converter

DVB Remultiplexer N-to-M

Hardware UDP/IP stack

RTP transmitter

Inputs/Ouputs

1 x UDP/IP input/output for MPEG TS input and IP cores registers configuration

(RJ45 connector on Xilinx SP605/ML605/KC705 board)

1 x IF/RF output (SMA connector on Digilent board)

Typical applications

Evaluation of MVD Cores’ IP cores (TS processing, Modulation, RF Up conversion)

圖5.AD9739A FMC評估板電路圖(1)

圖6.AD9739A FMC評估板電路圖(2)

圖7.AD9739A FMC評估板電路圖(3)

圖8.AD9739A FMC評估板電路圖(4)

圖9.AD9739A FMC評估板電路圖(5)
詳情請見(jiàn):
AD9737A_9739A.pdf (2.65 MB)

ad9739a-fmc-ebz_revb_schematic.pdf (345.06 KB)

來(lái)源:網(wǎng)絡(luò )
本文地址:http://selenalain.com/thread-94871-1-1.html     【打印本頁(yè)】

本站部分文章為轉載或網(wǎng)友發(fā)布,目的在于傳遞和分享信息,并不代表本網(wǎng)贊同其觀(guān)點(diǎn)和對其真實(shí)性負責;文章版權歸原作者及原出處所有,如涉及作品內容、版權和其它問(wèn)題,我們將根據著(zhù)作權人的要求,第一時(shí)間更正或刪除。
您需要登錄后才可以發(fā)表評論 登錄 | 立即注冊

相關(guān)視頻

關(guān)于我們  -  服務(wù)條款  -  使用指南  -  站點(diǎn)地圖  -  友情鏈接  -  聯(lián)系我們
電子工程網(wǎng) © 版權所有   京ICP備16069177號 | 京公網(wǎng)安備11010502021702
快速回復 返回頂部 返回列表
午夜高清国产拍精品福利|亚洲色精品88色婷婷七月丁香|91久久精品无码一区|99久久国语露脸精品|动漫卡通亚洲综合专区48页