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【獵頭職位：上海需要一位 CAD】聯(lián)系人：Raymond-Chen 郵箱：hr@kthr.com，微信也可查詢(xún)職位啦！打開(kāi)手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Responsibilities: 1. Developverification environment, including test bench and regression system creation,embed it in company customized design flow 2. Build testplan and verify the function of design, support gate level functionalverification, run coverage and regression. Analyze coverage gaps and devise strategyto fill coverage holes 3. Work closelywith different groups to review specification, improve verification plan andmethodology, and ensure full test coverage 4. InterfacingEDA vendors for tools' evaluation, assess vendors' design verificationcapabilities and convergence 5. CAD relateddocumentation. Requirements: 1. BSEE with 5+(or MSEE with 3+) years experience in ASIC verification, complex SOCverification experience is preferred. 2. Solidknowledge in verification methodology. Experience in verification using randomstimulus along with functional coverage and assertion-based verification method.Experience in UVM/OVM, object oriented design principles, Mentor Questasim SV,lower power verification flow with CPF/UPF. 3. Experiencein developing block and chip level test benches, test plan creation. 4. Good attiming analysis, practical skill with gate-level simulation and debuggingtechniques. 5. Familiarwith frontend EDA tools used in all phases of the frontend design cycle (suchas NC, RC, Conformal, ETS form Cadence; Or VCS, DC, Formality, PT fromSynopsys) is a plus. 6. Strongscript programming skills, such as Shell scripting, Perl and Tcl programming,to develop command scripts. 7.Self-motivated to drive for excellence. Must be a team player, and bedisciplined and well organized. 8. Excellentcommunication skills, and be able to work under schedule pressure. 
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