SOC Coherence Verification

發(fā)布時(shí)間:2018-7-6 11:32    發(fā)布者:KT咨詢(xún)
關(guān)鍵詞: Verification , Engineer

NO.469-【獵頭職位:上海需要一位  SOC Coherence Verification】聯(lián)系人:Grace-Tai,郵箱:hr@kthr.com,微信也可查詢(xún)職位了!打開(kāi)手機微信,搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加,歡迎大家關(guān)注!

Job Description:

Ø  Develop coherence verification platform

Ø  Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.

Ø  Work closely with the design group to identify problems

Ø  Hand-on experience in SOC coherence domain complex ASIC DV flow from plan to coverage

Job Requirement:

Ø  8+ years’ experience with Master degree or 10+ years’ experience with Bachelor degree.

Ø  Good knowledge in consistency and coherence consideration & design in SMP system

Ø  Experience with at least one complete and successful chip verification

Ø  Familiar with at least one coherent protocol like ACE, CHI, etc. is preferred

Ø  Experience with protocol and interconnect coherence verification is a big plus.

Ø  Proficient with Verilog, SystemVerilog

Ø  C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.

Ø  Expert in the use of Cadence/Synopsys verification tools, experience of Perspec is a plus

Ø  Experience with UVM/VMM methodologies is preferred

Ø  Strong documentation and communication skills.

Skills and Knowledge

Ø  Coherent Protocol

Ø  Verilog/System Verilog

Ø  UVM Verification Methodologies

Ø  C/C++

Ø  Perl, C Shell or Makefile

福利:五險一金


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