|
【獵頭職位：上海需要一位 Design Verification】聯(lián)系人：Grace-Tai，郵箱：hr@kthr.com，微信也可查詢(xún)職位啦！打開(kāi)手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Key responsibilities/duties: 1.Define testbench infrastructure using System Verilog, UVM and maybe Formal. 2.Assist in complete verification of high performance, high speed, low power ASIC. 3.Work closely with system architect and design managers to architect a new design verification environment and produce high quality verification closure. 4.Guide the development of comprehensive, flexible, and portable block to chip level testbench, detailed test plans and coverage closure. 5.Expert in industry I/O interface such as PCIe, USB, SERDESs and Ethernet etc. 6.Experienced in DSP or mix signal simulation is a big plus. 7.Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements. Requirements (indicate “must” or “preferred”) Key skills & knowledge: 1.Strong verification and technical lead skills including a good knowledge and understanding of different verification methodologies: ·random vs directed testing ·full chip vs module-level ·performance vs function ·error & drop handling 2.Past experience of successfully technically guiding complex, high speed design verification. 3.Experience with the following areas in design and verification: ·Advanced constrained-random function verification methodology such as UVM/VMM and/or SV Assertion. ·Systems using communication systems/protocols such as 802.3, PCIe, USB, serdes, 802.11, ARM. ·Formal verification with abstraction model for end-to-end checking. ·Low power verification with power gating and power management. ·Debug methodology 4.Self-motivated, good communicator, quick learner and good team player. 5.Display positive attitude and demonstrate flexibility in day-to-day work. Qualifications: MS/EE or CS with 3+ years of relevant experience. |
