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NO.400-【獵頭職位：上海、昆山需要多位 Staff Analog DesignEngineer-PLL】聯(lián)系人：Sophie-Song,郵箱：hr@kthr.com，微信也可查詢(xún)職位了！打開(kāi)手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ 崗位職責： 2、Oversee layout andverification activities which include floor plan, LVS and DRC. 崗位要求： 1、Minimum MSEE with 7+ years of relevant industry experience. 2、Good fundamental in analysis and design of analog / mixed-signalcircuits; Experience in Verilog, AHDL and/or Matlab; Ability to do layout andprovide verification/debugging guidance; Solid knowledge of EDA design tools(Analog artist, spectre, HSPICE and nc-verilog ...); Familiar with Computerlanguages such as C, C++, perl; 3、Experience in any of the following areas is preferred: PLL,high-speed I/O’s; 4、Good communication skills and Good oral/written English. 
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