High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting

發(fā)布時(shí)間：2014-7-16 17:08 發(fā)布者：看門(mén)狗

關(guān)鍵詞：信號完整性

High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting
Kyung Suk (Dan) Oh (Author), Xing Chao (Chuck) Yuan (Author)

Hardcover: 528 pages
Publisher: Prentice Hall; 1 edition (October 16, 2011)

內容簡(jiǎn)介：
New System-Level Techniques for Optimizing Signal/Power Integrity in High-Speed Interfaces--from Pioneering Innovators at Rambus, Stanford, Berkeley, and MIT As data communication rates accelerate well into the multi-gigahertz range, ensuring signal integrity both on- and off-chip has become crucial. Signal integrity can no longer be addressed solely through improvements in package or board-level design: Diverse engineering teams must work together closely from the earliest design stages to identify the best system-level solutions. In High-Speed Signaling, several of the field,s most respected practitioners and researchers introduce cutting-edge modeling, simulation, and optimization techniques for meeting this challenge. Edited by pioneering experts Drs. Dan Oh and Chuck Yuan, these contributors explain why noise and jitter are no longer separable, demonstrate how to model their increasingly complex interactions, and thoroughly introduce a new simulation methodology for predicting link-level performance with unprecedented accuracy. The authors address signal integrity from architecture through high-volume production, thoroughly discussing design, implementation, and verification. Coverage includes * New advances in passive-channel modeling, power-supply noise and jitter modeling, and system margin prediction* Methodologies for balancing system voltage and timing budgets to improve system robustness in high-volume manufacturing* Practical, stable formulae for converting key network parameters* Improved solutions for difficult problems in the broadband modeling of interconnects* Equalization techniques for optimizing channel performance* Important new insights into the relationships between jitter and clocking topologies* New on-chip measurement techniques for in-situ link performance testing* Trends and future directions in signal integrity engineering High-Speed Signaling thoroughly introduces new techniques pioneered at Rambus and other leading high-tech companies and universities: approaches that have never before been presented with this much practical detail. It will be invaluable to everyone concerned with signal integrity, including signal and power integrity engineers, high-speed I/O circuit designers, and system-level board design engineers.

PH_Jitter_Modeling_Analysis_Budgeting.part1.rar (14 MB)

PH_Jitter_Modeling_Analysis_Budgeting.part2.rar (14 MB)

PH_Jitter_Modeling_Analysis_Budgeting.part3.rar (14 MB)

PH_Jitter_Modeling_Analysis_Budgeting.part4.rar (14 MB)

PH_Jitter_Modeling_Analysis_Budgeting.part5.rar (14 MB)

PH_Jitter_Modeling_Analysis_Budgeting.part6.rar (12.85 MB)

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rinllow6 發(fā)表于 2014-7-17 12:49:51

謝謝�。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。�！

jimcmwang 發(fā)表于 2014-10-29 18:20:11

High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting

jimcmwang 發(fā)表于 2016-4-19 08:16:09

PH_Jitter_Modeling_Analysis_Budgeting.part1.rar (14 MB, 下載次數: 12)
  PH_Jitter_Modeling_Analysis_Budgeting.part2.rar (14 MB, 下載次數: 11)
  PH_Jitter_Modeling_Analysis_Budgeting.part3.rar (14 MB, 下載次數: 11)
  PH_Jitter_Modeling_Analysis_Budgeting.part4.rar (14 MB, 下載次數: 11)
  PH_Jitter_Modeling_Analysis_Budgeting.part5.rar (14 MB, 下載次數: 11)
  PH_Jitter_Modeling_Analysis_Budgeting.part6.rar (12.85 MB, 下載次數: 12)

myleshuzx 發(fā)表于 2016-10-14 16:51:47